Pipistrello as Logic Analyzer

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The Open Bench Logic Sniffer code has been ported to Pipistrello. This code is based on the original SUMP logic analyzer project.


See this link for info about the original SUMP logic analyser project written in VHDL.

See this link for info about Open Bench Logic Sniffer (derived from SUMP, ported to Verilog).

See this link for information about JaWi's Java-based SUMP client that runs on the PC.

Forum topic: Open Bench Logic Sniffer ported to Pipistrello LX45


Pipistrello code versions

The code exists in two different versions - Serial I/O version and FTDI async FIFO I/O version.

The serial I/O version works like the original Open Bench Logic Sniffer code but has increased data rate (912600 baud instead of 115200 baud). This version can be directly used by JaWi's SUMP client. The draw back is that the I/O data rate is relatively slow (about 100 KB/s).

The FTDI FIFO mode version can transfer data at much faster rate (up to about 8 MB/s) but this mode is not directly supported by most SUMP clients (like JaWi's SUMP client).


Modifications from the Open Bench Logic Sniffer code base

All the functionality of the Open Bench Logic Sniffer code remains but with the following additions/modifications:

  • The sample memory is increased from 24 KB to 64 MB using the on-board LPDDR memory
  • The ability to trigger on rising/falling edges in addition to high/low levels
  • Extensions to the SUMP protocol to increase the maximum sample count (the original SUMP protocol limits the sample count to 256K samples)
  • Increased I/O data rate


I/O Buffer board

The I/O pins on the Pipistrello board can only be used with logic levels up to 3.3V. To support 5V logic there is an add-on board that has 5V tolerant input buffers.

See this page for info about the buffer board.

File:Buffer small.jpg

The pin mapping is slightly different between the non-buffer versions and the buffer-versions of the code so you need to use a bit files designed for used with the buffer board.

It's strongly suggested that the buffer wing is used to protect the Pipistrello board input pins.


Bit files and source code

Bit files (all versions) are available here: Pipistrello_OLS_bitfiles.zip.

Verilog source code and Xilinx ISE project files are available here: Pipistrello_OLS_64M_src_08292014.zip


How to use with JaWi's SUMP client

The serial version can be used with the official release of the JaWi SUMP client with the following limitations:

  • Maximum sample count is 256K samples
  • Edge triggers are not supported


Steps to get it up and running:

1) Connect the Pipistrello board to the computer

2) Load or flash the correct bitfile to Pipistrello (serial, buffer or no-buffer version).

3) Start JaWi's SUMP client

4) Under the "Capture" pulldown menu, select "Begin capture". This will bring up the configuration menus

5) In the "Connection" tab:

  • set Connection type to Serial port
  • set Analyser port to the Pipistrello COM port
  • set Port Speed to 921600bps

6) To verify the connection press "Show device metadata" which should report that it found Pipistrello OLS 64M


Use the following steps to capture data some data:

7) In the "Acquisition" tab

  • set Number scheme to Inside
  • set Sampling clock to Internal
  • set Sampling rate to 100 MHz
  • enable all four Channel groups
  • set Recording Size to 128.00 k
  • enable Test mode (this will configure ch 16 - ch31 as outputs and driven with a test sequence)
  • disable Noise filter
  • disable Run Length Encoding

8) In the "Triggers" tab

  • disable Trigger
  • set Before/After ratio to 0

9) Press Capture


You should see the test sequence on ch 16 - 31 (just a binary counter).